A Compact Parallel Multiplication Scheme Based on (7,3) and (15,4) Self-timed Threshold Logic Counters
نویسندگان
چکیده
This paper presents a new, a highly compact implementation of a 32 32 parallel multiplier based on parallel counters. The new multiplier is designed using the recently proposed Self-Timed Threshold Logic (STTL). The design is based on a direct multiplication scheme using depth 2 (15,4) and (7,3) STTL parallel counters and (4:2) compressors. The proposed parallel multiplier reduces the partial product matrix to two rows in only three stages, hence the effective multiplier logic depth is 6. It is shown that the presented scheme significantly reduces the gate count of known proposals for multiplication using threshold logic.
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